Physical Design Webinars

In the recent past, I have hosted technical webinars on the following topics (in chronological order):

• Synthesis                                                    @ $20 (Lacks annotations)
• Essential DFT Fundamentals                @ $25 (Lacks annotations)
• STA (Part 1)                                                @ $40
• STA (Part 2)                                                @ $45
• Power Optimization Techniques        @ $35
• Power Gating                                            @ $35
• Special Physical Cells                              @ $20
• Antenna Effect                                         @ $20
• Signal Routing                                           @ $35
• Multi-Input Switching (MIS)                  @ $20
• CTS (Part 1)                                                @ $45
• CTS (Part 2)                                                @ $40
• Placement (Part 1)                                   @ $45 
• Placement (Part 2)                                   @ $40
• Crosstalk Analysis                                    @ $40
• EM/IR                                                            @ $45
• Power Estimation                                     @ $40 (Sep 27)

Future Topics:

• Synthesis 2.0
• Floorplanning
• Logical Equivalence Checking
• Low Power Checks (VCLP)
• Clock Domain Crossing
• DRC and LVS
• Machine Learning for PD

Past Mock Interviews (some slides only; some with solutions):

• PNR Mock (With Solutions)                                                  @ $40
• RCG Comp. Arch & PD Mock  (With Solutions)               @ $35 
• Power Analysis Mock                                                             @ $35

Scripting Module (With Solution Key):

• Physical Implementation Scripting (Tcl)                           @ $40
• Tool Independent Scripting (Tcl and Python)                 @ $40

The recordings of these webinars are available for purchase, and the prices may vary from time to time. Reach out to me to gain access to the recordings.

You can reach out to me via Discord or via email. 

• Discord: https://discord.gg/4RN7esTd3G (Username: metastable.design)
• Email: metastable01@gmail.com

In addition to technical webinars, I also offer tailor-made mock interviews for Physical Design, Implementation, STA, EM/IR and Power Optimization profiles.

Topic Lists:

1. SYNTHESIS

• Inputs/Outputs of Synthesis
• Synthesis Flow
• WNS and TNS Optimization Phases
• Path Groups
• WNS and TNS Optimization Phases for Path Groups
• Critical Range
• Weights
• Boundary Optimization
• Ungrouping
• Register Retiming
• Concurrent Clock and Data Optimization
• Scan Insertion and Scan Stitching
• Inputs/Outputs of Physical Synthesis
• Global Route for RC Estimation
• Register Banking
• Power Optimization using SAIF Files

2. Essential DFT Fundamentals:

• Why DFT?
• Types of Defect
• Fault Models
• Stuck-At Faults
• Quiz: Stuck-At Faults
• Scan Insertion
• Scan Chains
• Shift Mode and Capture Mode
• Clock Staggering
• Transition Faults
• At-Speed Capture
• Scan Chains Crossing Functional Clock Domains
• Lock-Up Latch
• Quiz: Scan Chain connections for posedge and negedge flops
• Quiz: Frequency of Shift Mode
• Controlling the Resets and Enables of ICGs
• CODEC
• Quiz: Scan Clock Multiplexing
• Timing Constraints
• Memory Testing
• Single v/s Split MBIST Controller
• MARCH Test for Memory Testing
• Bridging Faults and IDDQ Faults
• Path Delay Fault
• Test Point Insertion

3. STA (Part 1):

• Inputs and Outputs of STA
• Origin of Setup/Hold Time
• Quiz
• Timing Arcs
• NLDM Library: Combo Gates
• Timing Arcs: Setup and Hold
• NLDM Library: Interpolation and Extrapolation
• Clock Definitions
• Quiz
• Case Analysis
• Quiz
• Clock Gating Checks
• Integrated Clock Gating Cell
• Why are ICG Enable Paths Most Critical?
• Quiz
• Multi-cycle Paths
• MCP: Same Clock Frequency
• MCP: Different Clock Frequency | "start" option
• MCP: Different Clock Frequency | "end" option
• Quiz
• Clock Groups
• Reading a Timing Report- Setup
• Reading a Timing Report- Hold
• Hierarchical Block Implementation
• I/O Constraints
• Timing Report: In2Reg path
• Timing Report: Reg2Out path
• DRVs
• report_timing: max_paths vs nworst
• Quiz
• Validating Constraints
• check_timing
• report_analysis_coverage

4. STA (Part 2):

• GBA vs PBA
• Quiz
• PBA Mode: Path vs Exhaustive
• Quiz
• Miller Effect
• Long Tail Effect
• CCS Libraries
• CCS Libraries: Receiver Capacitance
• CCS Libraries: Recap
• set_driving_cell vs set_input_tran
• Common Path Pessimism Removal
• Impact of Crosstalk on Common Clock Path
• CPPR for half cycle paths
• Interconnect RC Corners
• Quiz
• Simultaneous Setup/Hold Critical Paths
• Negative Net delays
• OCV vs AOCV
• AOCV
• AOCV Path Depth with GBA vs PBA
• POCV
• POCV: LUT for sigma
• POCV Path Delay Calculation
• POCV Timing Report
• Crosstalk: Noise and Crosstalk Delay
• Crosstalk: Noise Immunity
• Latch Based Timing
• Quiz: Latch based timing

5. Power Optimization Techniques:

• Architectural Techniques:
• MV Design
• DVFS
• Power Gating
• Clock Gating
• Clock Gating: Timing vs Power
• Multi level Clock Gating
• ICG Cloning
• Data Bus Inversion Coding: DBI AC
• Data Bus Inversion Coding: DBI DC
• Datapath Restructuring and Datapath Gating
• Physical Design:
• Architectural ICG vs Inferred ICG
• Multi VT Synthesis
• Glitch Power
• Side Effects of Glitch Power
• Miscorrelation
• Register Banking
• Power Optimization using SAIF Files
• Self Gating (Data driven clock gating)
• Practical Use case of Self Gating
• Mixed Cell-Height Implementation
• Circuits
• Threshold Voltage
• Body Biasing
• Stack Effect
• Quiz x 2
  
  

6. Power Gating:

• Power Switches: Headers and Footers
• In-Rush Current
• Headers or Footers?
• Power Switch Placement
• In Rush Current vs Wake Up Time
• Star-Daisy Switch Chaining
• Mother-Daughter Configuration
• Hammer and Trickle Chains
• Hammer End Logic
• Power Switch with in-built buffer
• Power Switch with Separate Well
• State Retention Power Gating (SRPG)
• Isolation Cells
• Isolation Cells: Source or Destination

7. PNR Mock:

• Consists of a set of 15 analytical questions on circuits, synthesis, placement, CTS and routing to give an idea of practical questions that may be asked during the interviews. Comes with a solution set.

8. Special Physical Cells

• Decap Cells
• Tie Cells
• Filler Cells
• Tap Cells
• Latch-up (Recap)
• Endcaps/Boundary Cells
• ESD Clamps
• Die Level Process Monitors (DLPM)
• Quiz

9. Antenna Effect

• Antenna Effect
• Causes of Antenna
• Fixes for Antenna
• Cost of Antenna Fixing
• Quiz
• Reverse Antenna Effect
• NWELL Antenna Effect
  
  

10. Signal Routing

• Routing Sequence
• Virtual Routing
• Global Routing
• Global Routing Cell (GCELL)
• Global Routing Congestion (GRC)
• Timing Driven Global Routing
• Crosstalk Driven Global Routing
• Quiz
• RC Estimation Techniques
• Detail Routing
• Post Route Optimizations
• Redundant Via Insertion
• Antenna Fixing
• Dummy Metal Fill
• Wire Spreading
• Practical Guide to Debugging Route Results
• Maze Router (Lee's Algorithm)
• Recipe for Routing
• Routing Guides
• Routing Corridors
• Setting min/max Layer Constraints
• Via Ladder Insertion
• Identifying and Fixing Route Detours

11. Clock Tree Synthesis

• Objectives of CTS
• CTS Flow
• Design Initialization
• Primary CTS Corner
• Max Cap and Max Trans
• Clock Tree References
• Inverter vs Buffer Based Clock Tree + QUIZ
• Clock NDRs + QUIZ
• Clock Routing Layers
• Target Skew and Latency
• Max Fanout and Max Net Length
• Clock Cell Spacing Rules
• Clock Tree Topologies: Conventional CTS, MS-CTS and CTMesh Tradeoffs
• QUIZ
• Clock Balance Points
• Clock Skew Groups + QUIZ
• Concurrent Clock and Data Opt (CCD) + QUIZ
• Trial Clock Tree
• Clock Tree Exceptions
• Valid vs Invalid Clock Tree Network
• IO Latency postCTS
• Zero Clock Skew
• Clock Jitter: Factors Affecting Clock Jitter
• ICG Cloning and Merging

12. Clock Tree Synthesis (Part-2):

•  Part 2 discusses some common issues encountered while running CTS, and the potential solution space. Lots of interview questions and general discussion around CTS.

13. Placement (Part-1):

• Goal of Placement
• Placement Flow
• Placement Density Controls
• Detailed discussion on place.coarse.max_density
• Detailed discussion on place.coarse.congestion_driven_max_util
• Placement Control to meet a certain target routing density
• Path Group and Path Weights
• Placement Bounds
• Types of Placement Bounds
• Placement Attractions
• Placement Blockages
• Types of Placement Blockages
• Legalization
• How to debug Legalization Issues?
• Legalization Options
• Stream Legalization
• Congestion Driven Restructuring
• Register Banking
• Mixed Cell Height Implementation
• SAIF Based Placement
• Global Routing
• Global Routing Controls
• RC Estimation Techniques
• IR Aware Placement
• Scan Chain Reordering
• Relative Placement

14. Placement (Part -2):

• Part 2 discusses practical issues seen in real designs, and the possible solution space to the problems. These have been compiled from more than a decade's experience, and the audience would benefit from understanding potential issues and their solution space. The audience rated Part 2 far above Part 1 because that's something not readily available over the web.
  

15. Crosstalk Analysis:

• Why is Signal Integrity Important?
• Effects of Crosstalk
• Types of Noise
• Driver Weakening Effect
• Multi-Input Glitch
• Timing Window Overlap
• Techniques to Reduce Pessimism
• Crosstalk Delay Analysis Mode
• Composite Aggressors
• Logical Correlation
• Clock Groups and Clock Exclusivity
• Quiz x 2
• Aggressor Exclusion
• Noise Margins
• Noise Immunity
• Noise Slack
• Crosstalk Computation
• Noise Reporting Modes: Source vs Endpoint
• Crosstalk on Common Clock Path
• Crosstalk Miscorrelation: Top vs Tile
• Crosstalk Computation Algorithm
• Solving Crosstalk: Systematic and Pointed Fixes
• Quiz x 2

16. EM/IR:

• Inputs Needed for EM/IR Analysis
• What is IR Drop? Effects and Aftermath
• Static Drop
• Dynamic Drop
• Key Ingredients of IR drop analysis
• Power Grid Design: Implications on Power & Performance
• Effective Resistance
• Shortest Path Resistance
• Quiz
• Limitations with SPR
• BQM
• PeakTW
• Combining BQM with other checks
• Quiz
• Ways to Mitigate IR Drop
• IR Aware Placement
• Cell Spacing vs Cell Padding
• Cell Downsizing
• Power Grid Augmentation
• Decoupling Capacitors
• Dynamic Power Shaping
• Vector Based IR Analysis
• Voltage Stats Reporting: minTW, avgTW, eff-DVD
• Backside Power Delivery
• Quiz x 3
• Electromigration
• Factors Affecting EM
• Self Heating
• Wire Width, Wire Length affecting EM
• Types of EM Rules
• Frequency Dependence on EM
• Power EM vs Signal EM
• Fixing Power EM
• Fixing Signal EM
• Physically Broken Nets and Dropped Nets
• Quiz x 2
• Via Chopping Distance

Physical Implementation Scripting:

• Physical Implementation Scripting Module has 10 physical implementation tool based scripting problems that can make life of a physical designer easy. The problems are practical and has design aspects, gathering of data, making the reporting part efficient. For each problem, I have added a fair bit of background so that one feels motivated enough to write a script for the problem and as you would appreciate the problem statements are generic and something that people may encounter on a fairly regular basis. 
• The pre-requisite is: access to a tool and a postRoute design database. 
• Level: Mid senior to advanced level.
• The solution key will be based on the commands from the purple EDA vendor but can be ported over to the tools from other EDA vendors too. This module has the scripting problems as well as the solution key.

Tool Independent Scripting:

• This module includes 10 practical problems that can be solved using either Tcl or Python, focusing on file parsing tasks involving DEF, Verilog, reports, CSV, and .lib files to extract meaningful data programmatically. Some solutions are provided in Tcl, while others are in Python, offering flexibility to choose the language. 
• These problems are drawn from real-world scenarios encountered in day-to-day work, making them ideal for anyone looking to enhance their scripting skills for interviews or to establish a solid foundation in practical scripting. 
• All required input files and downloadable solutions are provided.