Physical Design Webinars

Technical Webinar Catalog

Metastable.Design

Deep-dive webinars on Physical Design, STA, Power, Synthesis and more — taught by practitioners, built for engineers who want to go beyond the basics.

💬 Discord: metastable.design ✉ metastable01@gmail.com

Available Recordings

20 topics

Essential DFT Fundamentals

Lacks annotations $25

• Why DFT?
• Types of Defect
• Fault Models
• Stuck-At Faults + Quiz
• Scan Insertion & Scan Chains
• Shift Mode and Capture Mode
• Clock Staggering
• Transition Faults
• At-Speed Capture
• Scan Chains Crossing Clock Domains
• Lock-Up Latch
• Quiz: posedge/negedge connections
• Controlling Resets/Enables of ICGs
• CODEC
• Timing Constraints
• Memory Testing
• Single vs Split MBIST Controller
• MARCH Test for Memory
• Bridging Faults and IDDQ Faults
• Path Delay Fault
• Test Point Insertion

Static Timing Analysis — Part 1

$40

• Inputs and Outputs of STA
• Origin of Setup/Hold Time + Quiz
• Timing Arcs
• NLDM Library: Combo Gates
• Timing Arcs: Setup and Hold
• NLDM: Interpolation & Extrapolation
• Clock Definitions + Quiz
• Case Analysis + Quiz
• Clock Gating Checks
• Integrated Clock Gating Cell
• Why ICG Enable Paths Are Critical + Quiz
• Multi-cycle Paths (Same & Different Freq)
• MCP: "start" and "end" options + Quiz
• Clock Groups
• Reading a Timing Report: Setup & Hold
• Hierarchical Block Implementation
• I/O Constraints
• Timing Report: In2Reg, Reg2Out
• DRVs
• report_timing: max_paths vs nworst
• Validating Constraints, check_timing
• report_analysis_coverage

Static Timing Analysis — Part 2

$45

• GBA vs PBA + Quiz
• PBA Mode: Path vs Exhaustive + Quiz
• Miller Effect
• Long Tail Effect
• CCS Libraries & Receiver Capacitance
• set_driving_cell vs set_input_tran
• Common Path Pessimism Removal
• Crosstalk on Common Clock Path
• CPPR for Half Cycle Paths
• Interconnect RC Corners + Quiz
• Simultaneous Setup/Hold Critical Paths
• Negative Net Delays
• OCV vs AOCV
• AOCV Path Depth with GBA vs PBA
• POCV: LUT for sigma, Path Delay, Timing Report
• Crosstalk: Noise and Crosstalk Delay
• Crosstalk Noise Immunity
• Latch Based Timing + Quiz

Power Optimization Techniques

$35

• MV Design & DVFS
• Power Gating & Clock Gating
• Clock Gating: Timing vs Power
• Multi-level Clock Gating
• ICG Cloning
• Data Bus Inversion (DBI AC & DC)
• Datapath Restructuring & Gating
• Architectural vs Inferred ICG
• Multi VT Synthesis
• Glitch Power & Side Effects
• Miscorrelation
• Register Banking
• Power Optimization with SAIF Files
• Self Gating (Data Driven Clock Gating)
• Mixed Cell-Height Implementation
• Threshold Voltage
• Body Biasing
• Stack Effect
• Quiz × 2

Power Gating

$35

• Power Switches: Headers and Footers
• In-Rush Current
• Headers or Footers?
• Power Switch Placement
• In Rush Current vs Wake Up Time
• Star-Daisy Switch Chaining
• Mother-Daughter Configuration
• Hammer and Trickle Chains
• Hammer End Logic
• Power Switch with In-built Buffer
• Power Switch with Separate Well
• State Retention Power Gating (SRPG)
• Isolation Cells: Source or Destination

Special Physical Cells

$20

• Decap Cells
• Tie Cells
• Filler Cells
• Tap Cells
• Latch-up (Recap)
• Endcaps / Boundary Cells
• ESD Clamps
• Die Level Process Monitors (DLPM)
• Quiz

Antenna Effect

$20

• Antenna Effect
• Causes of Antenna
• Fixes for Antenna
• Cost of Antenna Fixing
• Quiz
• Reverse Antenna Effect
• NWELL Antenna Effect

Signal Routing

$35

• Routing Sequence & Virtual Routing
• Global Routing & GCELL
• Global Routing Congestion (GRC)
• Timing & Crosstalk Driven Global Routing + Quiz
• RC Estimation Techniques
• Detail Routing
• Post Route Optimizations
• Redundant Via Insertion
• Antenna Fixing
• Dummy Metal Fill
• Wire Spreading
• Debugging Route Results
• Maze Router (Lee's Algorithm)
• Routing Guides & Corridors
• Min/Max Layer Constraints
• Via Ladder Insertion
• Fixing Route Detours

Multi-Input Switching (MIS)

$25

Recording available on request. Reach out via Discord or email to gain access.

Clock Tree Synthesis — Part 1

$45

• Objectives of CTS & CTS Flow
• Design Initialization
• Primary CTS Corner
• Max Cap and Max Trans
• Clock Tree References
• Inverter vs Buffer Based Clock Tree + Quiz
• Clock NDRs + Quiz
• Clock Routing Layers
• Target Skew and Latency
• Max Fanout and Max Net Length
• Clock Cell Spacing Rules
• CTS Topologies: Conventional, MS-CTS, CTMesh + Quiz
• Clock Balance Points
• Clock Skew Groups + Quiz
• Concurrent Clock and Data Opt (CCD) + Quiz
• Trial Clock Tree
• Clock Tree Exceptions
• Valid vs Invalid Clock Tree Network
• IO Latency postCTS
• Zero Clock Skew
• Clock Jitter Factors
• ICG Cloning and Merging

Clock Tree Synthesis — Part 2

$40

Covers common issues encountered while running CTS and the full solution space. Heavily interview-focused with practical discussion — a companion to Part 1 that goes well beyond textbook coverage.

Placement — Part 1

$45

• Goal of Placement & Placement Flow
• Placement Density Controls
• place.coarse.max_density (detailed)
• congestion_driven_max_util (detailed)
• Target Routing Density Control
• Path Groups and Path Weights
• Placement Bounds, Attractions & Blockages
• Legalization & Debugging
• Legalization Options & Stream Legalization
• Congestion Driven Restructuring
• Register Banking
• Mixed Cell Height Implementation
• SAIF Based Placement
• Global Routing Controls & RC Estimation
• IR Aware Placement
• Scan Chain Reordering
• Relative Placement

Placement — Part 2

$45

Covers practical issues seen in real designs, compiled from 10+ years of experience. Audience-rated above Part 1 — covers solution spaces not readily available online. Ideal for interview prep and real-world debugging.

Crosstalk Analysis

$40

• Why Signal Integrity Matters
• Effects of Crosstalk
• Types of Noise
• Driver Weakening Effect
• Multi-Input Glitch
• Timing Window Overlap
• Techniques to Reduce Pessimism
• Crosstalk Delay Analysis Mode
• Composite Aggressors
• Logical Correlation
• Clock Groups and Clock Exclusivity
• Quiz × 2
• Aggressor Exclusion
• Noise Margins, Immunity, Slack
• Crosstalk Computation
• Noise Reporting: Source vs Endpoint
• Crosstalk on Common Clock Path
• Crosstalk Miscorrelation: Top vs Tile
• Systematic & Pointed Fixes + Quiz × 2

EM / IR Drop Analysis

$45

• Inputs for EM/IR Analysis
• What is IR Drop? Effects
• Static & Dynamic Drop
• Key Ingredients of IR Analysis
• Power Grid Design Implications
• Effective & Shortest Path Resistance + Quiz
• BQM, PeakTW, Combinations + Quiz
• Ways to Mitigate IR Drop
• IR Aware Placement
• Cell Spacing vs Padding
• Cell Downsizing
• Power Grid Augmentation
• Decoupling Capacitors
• Dynamic Power Shaping
• Vector Based IR Analysis
• Voltage Stats: minTW, avgTW, eff-DVD
• Backside Power Delivery + Quiz × 3
• Electromigration Fundamentals
• Factors Affecting EM & Self Heating
• Wire Width & Length Effects on EM
• Types of EM Rules
• Frequency Dependence on EM
• Power EM vs Signal EM
• Fixing Power & Signal EM
• Physically Broken & Dropped Nets + Quiz × 2
• Via Chopping Distance

Power Estimation — Part 1

by Gigawatt $40

• Why Do Power Estimation?
• Types of Power for a Circuit
• Energy Stored in a Capacitor
• Why is Power Increasing? + Quiz × 2
• Inputs for Power Estimation + Quiz
• Power Analysis Modes + Quiz
• How Tools Calculate Switching Activity + Quiz
• Vector File Format (FSDB vs SAIF)
• Types of Activity Files
• Vector Based Power Analysis Modes
• Power Saving at Design Milestones
• RTL Power + Quiz
• Gate/Netlist Power with RTL Activity + Quiz
• Common Reports from Power Tool
• Activity File Generation
• When to Use Different Tests

Power Estimation — Part 2

by Gigawatt $45

• Energy-Delay Product Metric
• Energy vs Delay Tradeoff + Quiz
• Physical Design POV on Energy/Delay
• PVT Limitation on Power/Performance
• VF Curve + Quiz
• State Dependent Leakage Power + Quiz
• SDPD Based Power Estimation
• Pre-Si to Post-Si Power Correlation
• Simple CPU Power Model + Quiz
• RTL Power: Clock Enable Checker
• RTL Power: Register Data Checker
• RTL Power: Memory Power Checker
• RTL Power: MUX Power Checker
• RTL Power: Observability Don't Care
• RTL Power: Operand Isolation + Quiz

Synthesis 2.0 — Part 1

$40

• Inputs/Outputs of Logical Synthesis
• Synthesis Flow, Elaboration, Uniquification
• Linting Issues
• Liberty Files
• WNS/TNS Optimization Passes
• Path Groups, Critical Range & Weights
• Boundary Optimization
• Constant Propagation
• Register Retiming, Ungrouping
• Sequential Removal & Merging
• CCD
• Preferred MUX Implementation
• Register Replication + Quiz × 7
• RC Estimation during Synthesis
• Wire Load Models & Custom WLMs
• TLU+ File
• Scan Insertion & Scan Stitching
• Know Your Scan DEF
• DFT PREDRCs
• Zero Wire Load Timing Model

Synthesis 2.0 — Part 2

$45

• Inputs/Outputs of Physical Synthesis
• Physical Layout Estimation (PLE)
• Spatial Flow & iSpatial Flow (CRR)
• Global Routing
• Synthesis Timing Constraints
• Post-Synthesis Checks
• Triple Modular Redundancy (TMR)
• Providing RTL Feedback & Path Selection
• Understanding Critical Paths
• Power Optimization during Synthesis
• SAIF Files
• Clock Gating & Multi-Level CG
• Arch vs Inferred ICGs
• CG Style: Max Fan-Out, Min Bit Width + Quiz
• Cell/VT Selection during Synthesis
• Register Banking / MBCI
• Redundant Bit Removal
• Low Power Settings
• Feasibility Analysis & PPA Optimization
• Shmoo Plots, Perf/Leakage/Area Curves
• Flop Profiling

Unified Power Format (UPF) — Part 1

by Subhechcha Banerjee $45

• Components of Power
• LP Design Challenges
• Need for Unified Power Intent
• UPF History & UPF vs CPF
• Contents & Types of UPF
• Voltage Domain / Power Domain / Voltage Area
• Power Domains: UPF View
• Power Supply Network: UPF View
• Supply Sets and Handles
• NWELL Connection through Abutment
• Supply Sets: NWELL/PWELL + MCQ
• Macro / Hierarchical Cell Supply Connection
• Why set transitive true/false? + Quiz
• Power Supply States & Supply Level
• MCQ, Power State Tables, PST Case Study
• HighConn and LowConn Side of Ports
• Upper vs Lower Boundary
• Tool in Out-of-Context Mode
• Setting Context & Port Attributes
• MCQs × 2, Tips & Tricks

Phased Out

Synthesis (v1.0)

No longer available

EMIR 1.0

No longer available

Scripting Modules

with solution keys

Physical Implementation Scripting (Tcl)

$40

10 physical implementation tool-based scripting problems covering data gathering, design analysis and efficient reporting. Each problem includes detailed background and context. Solutions based on the purple EDA vendor — portable to others.

Pre-requisite: Tool access + postRoute design database  ·  Level: Mid-senior to advanced.

Tool Independent Scripting (Tcl + Python)

$40

10 practical file-parsing problems using Tcl or Python — DEF, Verilog, reports, CSV and .lib files. Drawn from real-world scenarios. Ideal for interview prep or scripting foundations. All input files and downloadable solutions included.

Mock Interviews

some with solutions

PNR MockWith Solutions

$40

15 analytical questions on circuits, synthesis, placement, CTS & routing.

RCG Comp. Arch & PD MockWith Solutions

$35

Power Analysis Mock 

$35

Analytical CMOS MockWith Solutions

$30

Tailor-made mock interviews also available for Physical Design, Implementation, STA, EM/IR and Power Optimization profiles. Reach out to discuss.

Coming Up

📅Fundamentals of UPFFeb 2026

📅Logical Equivalence CheckingFeb / Mar 2026

📅Low Power Checks (VCLP)Mar 2026

🔍Clock Domain CrossingBeing scoped

🔍Library CharacterizationBeing scoped

🙋FloorplanningSeeking experts

🙋Full Chip TimingSeeking experts

🙋DRC and LVSSeeking experts

🙋Machine Learning for PDSeeking experts

Want to host a webinar? If you're an experienced Design Verification engineer or into RTL design and willing to host, reach out at metastable01@gmail.com — we'd love to hear from you!
Access recordings: Contact via Discord (metastable.design) or email.