Interconnect RC Corners

While PVT corners are pretty straight forward to understand, many designers often feel confused with RC corners. In this post, I'll explain different RC corners that we need to sign-off our ASIC design on.

First try and understand the source of variations in R and C that lead to multiple RC corners. Some of the sources are:

1. Chemical Mechanical Planarization (CMP) process which removes the excess materials deposited while manufacturing.
2. Variability of photolithography equipment.
3. Some inconsistencies during the metal etching, where you might etch little bit more or little bit less which can directly impact the thickness of the interconnect wires.

Now, let’s take a look at the cross-section of semiconductor interconnects and see how does Resistance and Capacitance of the wires vary.

•  Resistance: Resistance depends on length and cross-section area, of course, with resistance being directly proportional to wire length, and being inversely proportional to the cross-section area. As temperature increases, resistance usually increases.
  
  
• Capacitance: It also depends on the interconnect dimensions and is directly proportional to the cross-section area and inversely proportional to the distance between the two wires. Physics 101. Ground and coupling capacitances.

Figure 1: Cross-section of a semiconductor inter-connects

While length is dependent on the design, other parameters are dependent on the technology node, where minimum wire-pitch, spacing, widths are defined in the tech-file. While discussing about RC corners, let’s limit our focus to the technology parameters: W, T, S and H.

Another important observation here is W and S are inversely correlated: increase in W means smaller S, and vice-versa. Rest all the parameters: W, T and H are uncorrelated. Variations in W and T manifest in different effects on Resistance and the capacitance. The wire delay, which is a rough function of R*C, is not a linear function of interconnect width.

Figure 2: Delay vs interconnect width

There may exist a sweet spot for interconnect width where R*C is minimum. Let’s call this W-opt. It would vary from one technology node to another. For widths smaller than the W-opt, resistance dominates in R*C and we would see maximum delay at W-min. For interconnect widths greater than W-opt, capacitance dominates in R*C and we would see maximum delay at W-max. For interconnect widths across W-opt, it might be difficult to say which corner: W-min or W-max would yield the worst delay value.

You might be looking for a straight forward answer, but you won’t find one here. J This story was important to help you connect the dots with the discussion on relative strength of aggressor and victim, and which case would produce the worst signal noise. The answer is it depends, and one cannot claim that a particular RC interconnect corner would always yield the worst noise results. It will depend a lot on the victim’s interconnect and aggressor’s switching characteristics. For example, now you understand how victim delay changes with interconnect parameters- W, T, H etc. Let’s say you performed a sensitivity analysis by changing the widths of the wires by delta amount.

W1 = W – ΔW and W2 = W + ΔW. If the delay of the wire is like:

Delay at width  W1 < Delay at width W < Delay at width W2, ... It means your wire lies in capacitance dominated region.

Similarly, if:

Delay at W1 > Delay at W > Delay at W2, ... Your wire lies in resistance dominated region.

Delay at W1 > Delay at W < Delay at W2, ... Your wire lies across the W-opt in the graph.

This explains how delays of wires changes across RC corners. We have 4 RC interconnect corners: Cmin, RCmin, Cmax, RCmax.

If your wire lies in the capacitance dominated region, it would be more susceptible to the impact of coupling capacitance, and hence any switching activity on the aggressor. Although, the noise may increase or decrease depending on the relative switching characteristics of aggressor and the victim, as discussed in the PVT corner section.

For example:

1.  RCmax: Although a bad design, but let’s say you have a very long wire (large L) in lower metal layers (small W, T) resistance would dominate and you would see the worst delay in the RCmax corner. RCmax is usually the most critical corner for setup timing closure. This would manifest when: Cc is minimum, and (R*Cg) is maximum.
   
   
2. RCmin: Let’s say you have many min paths in your design, and you’re looking for best delay numbers which can potentially result in hold time failures, you would look for RCmin corner, where you have many short nets (R would therefore be negligible), and capacitance would be minimum because of maximum spacing (S) and height (H). This would usually be the hold critical corner. Cc is maximum, and (R*Cg) is minimum.
   
   
3. Cmax: In presence of noise, you would want to check the corners with worst coupling capacitance. That would be your Cmax corner. This might also produce the worst delay for short nets for which resistance would be minimal. Cc is maximum.
   
   
4. Cmin: Cc is minimum, R is maximum and Cg is minimum. The short nets in min paths with minimal resistance (with or without aggressors) might see hold violations.

I was hoping no one would notice that in the table above, S and H are mentioned to be positively correlated, but in reality, and as also mentioned earlier, they are inversely correlated. This assumption might make the analysis more interesting, but I reckon EDA tools would assume the worst case and add additional pessimism in the timing analysis.

In a nutshell, it’s impossible to signoff noise at just one PVT or one interconnect corner. Also, designers take into account accurate aggressor switching activity in order to compute the worst noise impact. Assuming static aggressors, and taking into account only the coupling and the ground capacitance (Cc + Cg) may produce optimistic results, and subsequent failures on silicon.

References:

1.  “Parametric Analysis to Determine Accurate Interconnect Extraction Corners for Design Performance”, by Mutlu, Le, Molina and Celik. IEEE 2009.
2. “Interconnect Performance Corners considering Crosstalk Noise”, by Gandikota, Blaauw, Sylvester. IEEE 2009.