Latch-Up
CMOS device is often portrayed to be an impeccable device, especially in the textbooks. There are some innate problems in the CMOS device and one of them is the latch-up. We're gonna talk about it in detail. Consider the cross-section of a CMOS inverter. Please note that I have skipped drawing some metal layers and contacts for the sake of simplicity. My focus is on explaining the problem of latch-up and not the layout design rules! Figure 1: CMOS with parasitic BJTs In the above cross-section, note that 1-2-3 form a parasitic pnp type bipolar junction transistor, while 4-3-2 form a parasitic npn bipolar junction transistor. Since parasitic transistors would be present in every CMOS device! A simplistic figure depicting these parasitic transistors is given below: Figure 2: Simplistic Figure depicting parasitic BJTs Here, the npn and the pnp transistors are depicted with 2 and 3 being common between the two transistors. Also note that the n-well layer and the p-substrate ate lightl...
